mmSDMA0_UTCL1_INV1  116 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_UTCL1_INV1                                                                             0x0041
mmSDMA0_UTCL1_INV1  144 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_UTCL1_INV1	0x0041
mmSDMA0_UTCL1_INV1  142 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_UTCL1_INV1                                                                             0x0041
mmSDMA0_UTCL1_INV1  144 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_UTCL1_INV1                                                                             0x0041
mmSDMA0_UTCL1_INV1  144 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_UTCL1_INV1                                                                             0x0041