mmSDMA0_UTCL1_CNTL_BASE_IDX  107 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_UTCL1_CNTL_BASE_IDX                                                                    0
mmSDMA0_UTCL1_CNTL_BASE_IDX  135 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_UTCL1_CNTL_BASE_IDX	0
mmSDMA0_UTCL1_CNTL_BASE_IDX  133 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_UTCL1_CNTL_BASE_IDX                                                                    0
mmSDMA0_UTCL1_CNTL_BASE_IDX  135 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_UTCL1_CNTL_BASE_IDX                                                                    0
mmSDMA0_UTCL1_CNTL_BASE_IDX  135 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_UTCL1_CNTL_BASE_IDX                                                                    0