mmSDMA0_ULV_CNTL_BASE_IDX  203 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_ULV_CNTL_BASE_IDX	0
mmSDMA0_ULV_CNTL_BASE_IDX  199 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_ULV_CNTL_BASE_IDX                                                                      0
mmSDMA0_ULV_CNTL_BASE_IDX  201 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_ULV_CNTL_BASE_IDX                                                                      0
mmSDMA0_ULV_CNTL_BASE_IDX  199 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_ULV_CNTL_BASE_IDX                                                                      0