mmSDMA0_STATUS_REG_BASE_IDX   61 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_STATUS_REG_BASE_IDX                                                                    0
mmSDMA0_STATUS_REG_BASE_IDX   89 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_STATUS_REG_BASE_IDX	0
mmSDMA0_STATUS_REG_BASE_IDX   87 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_STATUS_REG_BASE_IDX                                                                    0
mmSDMA0_STATUS_REG_BASE_IDX   89 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_STATUS_REG_BASE_IDX                                                                    0
mmSDMA0_STATUS_REG_BASE_IDX   89 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_STATUS_REG_BASE_IDX                                                                    0