mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX  878 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX                                                               0
mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX  895 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX                                                               0
mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX  891 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX                                                               0