mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 796 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x0327 mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 812 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x02ef mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 808 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x0327