mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX  838 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX  855 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX  851 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0