mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI  837 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x0352
mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI  854 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI  850 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x0352