mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX  801 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX  817 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX  813 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          0