mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX  844 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0
mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX  861 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0
mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX  857 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0