mmSDMA0_RLC3_RB_WPTR_POLL_CNTL  630 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL                                                                 0x0267
mmSDMA0_RLC3_RB_WPTR_POLL_CNTL  644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
mmSDMA0_RLC3_RB_WPTR_POLL_CNTL  640 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL                                                                 0x0267