mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI  671 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x0292
mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI  686 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI  682 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x0292