mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX  548 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX  561 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX  557 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0