mmSDMA0_RLC1_STATUS_BASE_IDX  489 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC1_STATUS_BASE_IDX                                                                   0
mmSDMA0_RLC1_STATUS_BASE_IDX  501 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_RLC1_STATUS_BASE_IDX	0
mmSDMA0_RLC1_STATUS_BASE_IDX  413 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_RLC1_STATUS_BASE_IDX                                                                   0
mmSDMA0_RLC1_STATUS_BASE_IDX  501 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC1_STATUS_BASE_IDX                                                                   0
mmSDMA0_RLC1_STATUS_BASE_IDX  497 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC1_STATUS_BASE_IDX                                                                   0