mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX  467 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX  479 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX	0
mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX  391 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX  479 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX  475 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          0