mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX  516 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX                                                             0
mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX  529 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX	0
mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX  441 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX                                                             0
mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX  529 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX                                                             0
mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX  525 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX                                                             0