mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX  376 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX                                                               0
mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX  387 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX	0
mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX  299 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX                                                               0
mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX  387 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX                                                               0
mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX  383 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX                                                               0