mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX  437 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX                                                             0
mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX  449 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX	0
mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX  361 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX                                                             0
mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX  449 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX                                                             0
mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX  445 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX                                                             0