mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX  431 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX                                                             0
mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX  443 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX	0
mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX  355 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX                                                             0
mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX  443 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX                                                             0
mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX  439 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX                                                             0