mmSDMA0_RLC0_DOORBELL_BASE_IDX  404 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_RLC0_DOORBELL_BASE_IDX                                                                 0
mmSDMA0_RLC0_DOORBELL_BASE_IDX  415 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_RLC0_DOORBELL_BASE_IDX	0
mmSDMA0_RLC0_DOORBELL_BASE_IDX  327 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_RLC0_DOORBELL_BASE_IDX                                                                 0
mmSDMA0_RLC0_DOORBELL_BASE_IDX  415 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_RLC0_DOORBELL_BASE_IDX                                                                 0
mmSDMA0_RLC0_DOORBELL_BASE_IDX  411 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_RLC0_DOORBELL_BASE_IDX                                                                 0