mmSDMA0_PHASE1_QUANTUM_BASE_IDX   77 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX                                                                0
mmSDMA0_PHASE1_QUANTUM_BASE_IDX  105 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX	0
mmSDMA0_PHASE1_QUANTUM_BASE_IDX  103 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX                                                                0
mmSDMA0_PHASE1_QUANTUM_BASE_IDX  105 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX                                                                0
mmSDMA0_PHASE1_QUANTUM_BASE_IDX  105 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX                                                                0