mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX  344 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX                                                              0
mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX  355 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX	0
mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX  355 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX                                                              0
mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX  351 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX                                                              0