mmRMI_UTCL1_CNTL2_BASE_IDX 3097 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRMI_UTCL1_CNTL2_BASE_IDX                                                                     0
mmRMI_UTCL1_CNTL2_BASE_IDX 1092 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRMI_UTCL1_CNTL2_BASE_IDX                                                                     0
mmRMI_UTCL1_CNTL2_BASE_IDX 1099 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRMI_UTCL1_CNTL2_BASE_IDX                                                                     0
mmRMI_UTCL1_CNTL2_BASE_IDX 1065 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRMI_UTCL1_CNTL2_BASE_IDX                                                                     0