mmRMI_UTCL1_CNTL1_BASE_IDX 3095 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRMI_UTCL1_CNTL1_BASE_IDX                                                                     0
mmRMI_UTCL1_CNTL1_BASE_IDX 1090 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRMI_UTCL1_CNTL1_BASE_IDX                                                                     0
mmRMI_UTCL1_CNTL1_BASE_IDX 1097 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRMI_UTCL1_CNTL1_BASE_IDX                                                                     0
mmRMI_UTCL1_CNTL1_BASE_IDX 1063 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRMI_UTCL1_CNTL1_BASE_IDX                                                                     0