mmRLC_UTCL1_STATUS_BASE_IDX 9585 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_UTCL1_STATUS_BASE_IDX                                                                    1
mmRLC_UTCL1_STATUS_BASE_IDX 6255 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_UTCL1_STATUS_BASE_IDX                                                                    1
mmRLC_UTCL1_STATUS_BASE_IDX 6499 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_UTCL1_STATUS_BASE_IDX                                                                    1
mmRLC_UTCL1_STATUS_BASE_IDX 6475 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_UTCL1_STATUS_BASE_IDX                                                                    1