mmRLC_UTCL1_STATUS_2_BASE_IDX 9533 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_UTCL1_STATUS_2_BASE_IDX                                                                  1
mmRLC_UTCL1_STATUS_2_BASE_IDX 6201 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_UTCL1_STATUS_2_BASE_IDX                                                                  1
mmRLC_UTCL1_STATUS_2_BASE_IDX 6445 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_UTCL1_STATUS_2_BASE_IDX                                                                  1
mmRLC_UTCL1_STATUS_2_BASE_IDX 6421 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_UTCL1_STATUS_2_BASE_IDX                                                                  1