mmRLC_UTCL1_STATUS_2 9532 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_UTCL1_STATUS_2                                                                           0x4cb6
mmRLC_UTCL1_STATUS_2 6200 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_UTCL1_STATUS_2                                                                           0x4cb6
mmRLC_UTCL1_STATUS_2 6444 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_UTCL1_STATUS_2                                                                           0x4cb6
mmRLC_UTCL1_STATUS_2 6420 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_UTCL1_STATUS_2                                                                           0x4cb6