mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 9543 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX                                                               1
mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 6211 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX                                                               1
mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 6455 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX                                                               1
mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX 6431 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX                                                               1