mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 9541 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX                                                               1
mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 6209 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX                                                               1
mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 6453 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX                                                               1
mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX 6429 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX                                                               1