mmRLC_SPM_UTCL1_CNTL_BASE_IDX 9531 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_SPM_UTCL1_CNTL_BASE_IDX                                                                  1
mmRLC_SPM_UTCL1_CNTL_BASE_IDX 6199 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_SPM_UTCL1_CNTL_BASE_IDX                                                                  1
mmRLC_SPM_UTCL1_CNTL_BASE_IDX 6443 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_SPM_UTCL1_CNTL_BASE_IDX                                                                  1
mmRLC_SPM_UTCL1_CNTL_BASE_IDX 6419 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_SPM_UTCL1_CNTL_BASE_IDX                                                                  1