mmRLC_SPM_UTCL1_CNTL 9530 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_SPM_UTCL1_CNTL                                                                           0x4cb5
mmRLC_SPM_UTCL1_CNTL 6198 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_SPM_UTCL1_CNTL                                                                           0x4cb5
mmRLC_SPM_UTCL1_CNTL 6442 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_SPM_UTCL1_CNTL                                                                           0x4cb5
mmRLC_SPM_UTCL1_CNTL 6418 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_SPM_UTCL1_CNTL                                                                           0x4cb5