mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 9059 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX                                                              1
mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 5813 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX                                                              1
mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 6065 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX                                                              1
mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 6025 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX                                                              1