mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 9045 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX                                                        1
mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 5803 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX                                                        1
mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 6055 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX                                                        1
mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 6015 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX                                                        1