mmRLC_SPM_PERFMON_CNTL_BASE_IDX 9043 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_SPM_PERFMON_CNTL_BASE_IDX                                                                1
mmRLC_SPM_PERFMON_CNTL_BASE_IDX 5801 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_SPM_PERFMON_CNTL_BASE_IDX                                                                1
mmRLC_SPM_PERFMON_CNTL_BASE_IDX 6053 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_SPM_PERFMON_CNTL_BASE_IDX                                                                1
mmRLC_SPM_PERFMON_CNTL_BASE_IDX 6013 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_SPM_PERFMON_CNTL_BASE_IDX                                                                1