mmRLC_SPM_INT_CNTL 9432 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_SPM_INT_CNTL                                                                             0x4c72
mmRLC_SPM_INT_CNTL 6090 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_SPM_INT_CNTL                                                                             0x4c72
mmRLC_SPM_INT_CNTL 6334 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_SPM_INT_CNTL                                                                             0x4c72
mmRLC_SPM_INT_CNTL 6312 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_SPM_INT_CNTL                                                                             0x4c72
mmRLC_SPM_INT_CNTL 1324 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmRLC_SPM_INT_CNTL                                                      0x3132
mmRLC_SPM_INT_CNTL 1337 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmRLC_SPM_INT_CNTL                                                      0x3132
mmRLC_SPM_INT_CNTL 1439 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmRLC_SPM_INT_CNTL                                                      0xec72
mmRLC_SPM_INT_CNTL 1436 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmRLC_SPM_INT_CNTL                                                      0xec72