mmRLC_SMU_MESSAGE_BASE_IDX 9437 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_SMU_MESSAGE_BASE_IDX                                                                     1
mmRLC_SMU_MESSAGE_BASE_IDX 6095 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_SMU_MESSAGE_BASE_IDX                                                                     1
mmRLC_SMU_MESSAGE_BASE_IDX 6339 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_SMU_MESSAGE_BASE_IDX                                                                     1
mmRLC_SMU_MESSAGE_BASE_IDX 6317 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_SMU_MESSAGE_BASE_IDX                                                                     1