mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 9389 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX                                                          1
mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 6045 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX                                                          1
mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 6289 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX                                                          1
mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX 6265 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX                                                          1