mmRLC_SMU_COMMAND_BASE_IDX 9507 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_SMU_COMMAND_BASE_IDX                                                                     1
mmRLC_SMU_COMMAND_BASE_IDX 6175 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_SMU_COMMAND_BASE_IDX                                                                     1
mmRLC_SMU_COMMAND_BASE_IDX 6419 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_SMU_COMMAND_BASE_IDX                                                                     1
mmRLC_SMU_COMMAND_BASE_IDX 6395 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_SMU_COMMAND_BASE_IDX                                                                     1