mmRLC_RLCV_TIMER_STAT 10336 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_RLCV_TIMER_STAT                                                                          0x5b27
mmRLC_RLCV_TIMER_STAT 6760 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_RLCV_TIMER_STAT                                                                          0x5b27
mmRLC_RLCV_TIMER_STAT 7008 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_RLCV_TIMER_STAT                                                                          0x5b27
mmRLC_RLCV_TIMER_STAT 7044 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_RLCV_TIMER_STAT                                                                          0x5b27