mmRLC_RLCV_TIMER_CTRL_BASE_IDX 10335 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_RLCV_TIMER_CTRL_BASE_IDX                                                                 1
mmRLC_RLCV_TIMER_CTRL_BASE_IDX 6759 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_RLCV_TIMER_CTRL_BASE_IDX                                                                 1
mmRLC_RLCV_TIMER_CTRL_BASE_IDX 7007 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_RLCV_TIMER_CTRL_BASE_IDX                                                                 1
mmRLC_RLCV_TIMER_CTRL_BASE_IDX 7043 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_RLCV_TIMER_CTRL_BASE_IDX                                                                 1