mmRLC_RLCV_SPARE_INT 9632 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_RLCV_SPARE_INT                                                                           0x4d00
mmRLC_RLCV_SPARE_INT 6270 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_RLCV_SPARE_INT                                                                           0x4f30
mmRLC_RLCV_SPARE_INT 6514 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_RLCV_SPARE_INT                                                                           0x4f30
mmRLC_RLCV_SPARE_INT 6524 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_RLCV_SPARE_INT                                                                           0x4f30