mmRLC_PG_CNTL_BASE_IDX 9355 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_PG_CNTL_BASE_IDX                                                                         1
mmRLC_PG_CNTL_BASE_IDX 6011 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_PG_CNTL_BASE_IDX                                                                         1
mmRLC_PG_CNTL_BASE_IDX 6255 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_PG_CNTL_BASE_IDX                                                                         1
mmRLC_PG_CNTL_BASE_IDX 6231 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_PG_CNTL_BASE_IDX                                                                         1