mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 6039 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX                                                            1
mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 6283 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX                                                            1
mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX 6259 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX                                                            1