mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 9351 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX                                                            1
mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 6007 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX                                                            1
mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 6251 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX                                                            1
mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 6227 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX                                                            1