mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 9555 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX                                                           1
mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 6223 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX                                                           1
mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 6467 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX                                                           1
mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX 6443 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX                                                           1