mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 9553 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX                                                           1
mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 6221 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX                                                           1
mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 6465 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX                                                           1
mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX 6441 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX                                                           1