mmRLC_GPM_UTCL1_CNTL_2 9528 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_GPM_UTCL1_CNTL_2                                                                         0x4cb4
mmRLC_GPM_UTCL1_CNTL_2 6196 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_GPM_UTCL1_CNTL_2                                                                         0x4cb4
mmRLC_GPM_UTCL1_CNTL_2 6440 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_GPM_UTCL1_CNTL_2                                                                         0x4cb4
mmRLC_GPM_UTCL1_CNTL_2 6416 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_GPM_UTCL1_CNTL_2                                                                         0x4cb4