mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 9527 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX                                                                1
mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 6195 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX                                                                1
mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 6439 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX                                                                1
mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX 6415 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX                                                                1