mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 9525 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX                                                                1
mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 6193 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX                                                                1
mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 6437 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX                                                                1
mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX 6413 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX                                                                1