mmRLC_GPM_UTCL1_CNTL_0 9524 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmRLC_GPM_UTCL1_CNTL_0                                                                         0x4cb2
mmRLC_GPM_UTCL1_CNTL_0 6192 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmRLC_GPM_UTCL1_CNTL_0                                                                         0x4cb2
mmRLC_GPM_UTCL1_CNTL_0 6436 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmRLC_GPM_UTCL1_CNTL_0                                                                         0x4cb2
mmRLC_GPM_UTCL1_CNTL_0 6412 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmRLC_GPM_UTCL1_CNTL_0                                                                         0x4cb2